This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-57376 filed on Mar. 1, 2001, Japanese Patent Application No. 2001-260644 filed on Aug. 30, 2001, Japanese Patent Application No. 2001-401293 filed on Dec. 28, 2001 and Japanese Patent Application No. 2001-378778 filed on Dec. 12, 2001; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device with the reliability of connection by bonding or the like improved and its manufacturing method.
2. Description of the Related Art
Recently, with the increase of the integration degree and operation velocity of the semiconductor device, copper (hereinafter called as xe2x80x9cCuxe2x80x9d) is used instead of aluminum (Al) or the like as a wiring material from the viewpoint of the reduction in resistance and high reliability of each wiring layer. The technology, which uses Cu as a wiring material, is increasing in importance for speed-up of the semiconductor device and the increase in stacked layers of a wiring structure with the advance of a microfabrication technology.
In the assembly process of a semiconductor device, a bonding step is performed to electrically connect each wiring layer of the semiconductor device and an outside conductive substance (e.g., a bonding pad of a package) via a metal wire or a conductive substance such as conductive bump. To perform the bonding step, a pad electrode layer and a metal wire or conductive bump of the semiconductor device are directly connected so to electrically conduct the respective wiring layers of the semiconductor device and the outside conductive substance. Specifically, the metal wire (e.g., gold (Au)) is directly bonded to the pad electrode layer or the conductive bump are formed on the pad electrode layer to make flip-chip connection.
Since the pad electrode layer is formed as apart of wiring on the top layer, the same material as the wiring layer of the semiconductor device is used. Therefore, Cu is conveniently used instead of Al or the like as a material for the pad electrode layer in the same way as the other wiring layer in view of reduction of the number of steps.
When a thermal treatment is performed with the top layer of the Cu wiring layer exposed to the atmosphere in order to form the pad electrode layer, the Cu wiring layer is readily oxidized from its surface to inside. Therefore, when Cu is used as a pad material, the bonding step cannot be performed while heating in the atmosphere by a conventional apparatus. In this case, the bonding step can be performed in a flow of nitrogen or hydrogen or in a non-oxidizing atmosphere or a reducing atmosphere with the surface of the pad electrode layer prevented from being oxidized, but it is necessary to make a major modification of the apparatus. In a step of heating treatment after the bonding, there is also a problem that a bonded part becomes defective because oxidation continues.
In connection with the above problems, Japanese Patent Laid-Open Application No. Hei 9-92649 JP-A discloses a method of forming an oxidation-resistant and corrosion-resistant protective layer on a copper wiring structure or a copper electrode pad structure (=copper pad electrode layer) within an opening.
It discloses a method of forming a copper-aluminum alloy layer (hereinafter called as xe2x80x9cCuxe2x80x94Al alloy layerxe2x80x9d) on the surface of a Cu wiring layer by forming an aluminum film (hereinafter called as xe2x80x9cAl filmxe2x80x9d) having a thickness of about 2% or less of that of the Cu film on a copper film (hereinafter called as xe2x80x9cCu filmxe2x80x9d) configuring wires and a pad electrode and on an insulating film around it and performing a thermal treatment. Thus, there is disclosed a method of improving the reliability of the wiring structure or the pad electrode structure by forming an alloy film of a metal containing Al and preventing the Cu wiring layer from being oxidized or corroded.
Japanese Patent Laid-Open Application No. Hei 9-92649 JP-A discloses a subsequent method of wet-etching to remove the unreacted Al film remained on the insulating film with diluted hydrofluoric acid or phosphoric acid and thermally treating the Cu wiring layer in a mixture gas of hydrogen and oxygen or hydrogen and steam. Here, the Cu wiring layer is thermally treated again to form a thin film containing Al and oxygen or a thin oxide film containing Al, Cu and oxygen on the surface of the Cuxe2x80x94Al alloy layer. Thus, the reliability of the Cu wiring or the Cu electrode pad structure can be improved.
It is necessary to minimize the thickness of the Cu alloy film in order to suppress the resistance value of the pad electrode layer (e.g., Cu) from increasing. Accordingly, it is thinkable that the metal film (e.g., Al) formed on the pad electrode layer is made to be thin as small as possible.
Therefore, Japanese Patent Laid-Open Application No. Hei 9-92649 JP-A needs make the Cuxe2x80x94Al alloy layer thinner as small as possible in order to suppress the resistance value of the Cu electrode pad structure (=Cu pad electrode layer) from increasing. Thus, it is conceivable that the Al film is formed in a thickness as small as possible on the Cu film configuring the electrode pad structure.
However, if the metal film (e.g., Al) formed on the pad electrode layer is excessively thin, the following problems occur.
For example, the metal film agglomerates to have a spherical shape on the periphery of the pad electrode layer (=wiring layer on the top layer), namely on the insulating film such as a passivation film by the thermal treatment in the process of forming the alloy film on the pad electrode layer, and the metal layer has an increased thickness (corresponding to a diameter of the sphere).
In this case, an unnecessary portion of the metal film remained on the insulating film around the pad electrode layer is removed by a wet etching process or a CMP method (=chemical-mechanical polishing method), etc., but there is a problem that the processing time becomes long and a practical process margin cannot be obtained.
After the electrode pad of the Cu wiring structure is formed, a silicon wafer is generally inspected before an assembly process is performed to connect to an outside conductive substance (e.g., package bonding pad) through a conductive substance such as a metal wire (e.g., gold (Au)) or conductive bump. Here, a probing needle is contacted to the pad electrode layer of each semiconductor chip to inspect in the atmosphere so that a judgment is made to select a good chip only. After the inspection, only the good chips are subjected to the assembly process.
In this case, there comes a scratch of certain depth in the pad electrode layer when the pad electrode layer is contacted by the probing needle because it has a sharp tip. Therefore, when the pad electrode layer has a structure that the protective layer is formed on the Cu wiring layer, the probing needle breaks through the protective layer to reveal the Cu wiring layer located below it, resulting in oxidation in the later assembly step. Therefore, there is also a problem that a metal oxide layer on the pad electrode layer is readily cut away by the probing needle, and the oxidation resistance of the pad electrode layer is degraded.
Before the assembly step, a thermal treatment may be performed to form an oxidizing protective layer again on the scratch caused by the probing needle so to protect the pad electrode layer. However, it is impossible to form the metal oxide layer again because a metal required to form the metal oxide layer as the protective layer is not enough contained in the Cu wiring layer located on a lower layer. In the assembly step, particularly in the bonding step or the like, a bonding strength and conductivity become defective when the metal wire or conductive bump are connected to such pad electrode.
Thus, to form the pad electrode layer, it is necessary to consider not only the suppression of the wiring resistance value, oxidation resistance and corrosion resistance but also an effect on the later steps, such as a step of removing the unnecessary metal film, a wafer inspection step, a bonding step and the like.
Therefore, even the method disclosed in Japanese Patent Laid-Open Application No. Hei 9-92649 JP-A needs to consider an effect on the suppression of the wiring resistance value, the wafer inspection step, the bonding step and the like in forming the Cu electrode pad structure (=Cu pad electrode layer). For example, formation of the protective layer is not limited on the surface layer only by forming a material (=Al) on the Cu wiring layer, but it is necessary to form the Cuxe2x80x94Al alloy layer into the pad electrode layer though the resistance value of the pad electrode layer increases in order to secure the oxidation resistance and corrosion resistance of the entire pad electrode layer.
However, the method disclosed in Japanese Patent Laid-Open Application No. Hei 9-92649 JP-A merely puts emphasis on the formation of the Al film in a thickness as small as possible to form the Cu electrode pad structure so to suppress the resistance value from increasing but does not consider the aforementioned points.
Next, problems related to the inspection step of the silicon wafer by the prober will be further described. FIG. 25 is a diagram showing a cross section of the wiring pad structure as an example of prior art using the Cu multilayer wiring.
This prior wiring pad structure has an Al cap film 73 formed on a Cu pad 71 embedded in the surface of an insulating film 70 via a barrier metal film 72. The Al cap film 73 is to prevent the Cu pad 71 from being oxidized. In the figure, reference numerals 74, 75 denote insulating films. The Al cap film 73 contains, for example, Al as a main component and also a small amount of Cu (e.g., 0.5 wt %).
However, the conventional wiring pad structure has the following problems. Specifically, a probing needle 77 comes in contact with the Al cap film 73 about ten times if many in the probing step as shown in FIG. 26, the Al cap film 73 is broken due to delamination to expose the Cu pad 71 to the atmosphere, and the Cu pad 71 is broken if excessively contacted.
In case of the exposure to the atmosphere or breakage as described above, the exposed Cu pad 71 is oxidized, or a compound is produced by a reaction between Cu in the exposed Cu pad 71 and Al in the Al cap film 73.
As a result, there is a problem that the wire bonding resistance is degraded or the pad section has a greatly increased resistance. Besides, when oxidation reaches the deep section of the wiring layer, a problem such as fatal deterioration occurs in the wiring characteristic such as electro-migration (EM) resistance, stress migration (SM) resistance or the like in addition to the aforementioned problem.
As described above, the conventional wiring pad structure might have the Al cap film broken when contacted by the probing needle in the probing step, and the Cu pad may be revealed or broken. Thus, it is probable that the wire bonding resistance is degraded, the resistance of the pad section is increased, and the wiring characteristics such as the EM resistance or the SM resistance are fatally degraded.
Then, problems of a semiconductor device using the Cu wiring which has as the pad structure a Cu layer and an Al layer as its upper layer and a barrier metal layer disposed between the Cu layer and the Al layer will be described.
When a semiconductor device has a multilayer wiring structure having wiring on multiple layers, for example, the surface (exposed surface) of wiring formed on the top layer is used as a wiring pad for external connection. When the wiring is formed of Cu, the protective conducting layer excelling in resistance to oxidation is generally used as a cap film to protect the Cu layer (Cu wiring) because Cu is not resistant to oxidation, and especially the Al film is used as a cap film.
However, Al and Cu are highly reactive, so that when the Al cap film is directly stacked on the Cu surface, there is a problem that an intermetallic compound is formed and a resistance is increased by the subsequent major step which is a passivation deposition step or a thermal process such as a connection step by bump connection or wire bonding. To avoid such a problem, a Ta-based or Ti-based barrier metal film is generally disposed between the Cu wiring and the Al cap film.
The barrier metal film is required to have a mechanical strength to external forces such as probing, wire bonding and the like in addition to the aforementioned Cu, Al diffusion barrier properties. But, there may be a problem that the barrier metal film having a general laminated structure formed of two layers of Ta2N and Ta is sheared due to delamination caused when probing. In the barrier metal forming process, there may be a problem that dust (particles) increases in the sputtering step when a layer of Ta2N of the Ta-based barrier metal is made thick, and the barrier properties are degraded due to existance of the dust.
A semiconductor device according to an embodiment of the present invention is comprised of a copper wiring layer formed above a semiconductor substrate; a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy containing copper and a metal having a higher oxidation tendency than copper formed to reach bottom surface of the pad electrode layer; and an insulating protective film having an opening extended to the pad electrode layer.
A method of manufacturing a semiconductor device according to an embodiment of the present invention is comprised of forming an insulating film above a semiconductor substrate; forming a copper wiring layer in the insulating film; forming an insulating protective film on the copper wiring layer; forming an opening extended to the copper wiring layer in the insulating protective layer; forming a film of a metal having a higher oxidation tendency than copper or a film of an alloy containing a metal having a higher oxidation tendency than the copper on the copper wiring layer in the opening; and performing a thermal treatment to diffuse the metal or the alloy in the copper wiring layer so that an alloy containing copper and a metal whose oxidation tendency is higher than copper extended to the bottom surface of the copper wiring layer is formed to form a pad electrode layer, and an oxide layer mainly comprising the metal on the surface layer of the pad electrode layer is formed.
Another method of manufacturing a semiconductor device according to an embodiment of the invention is comprised of forming an insulating film above a semiconductor substrate; forming a copper wiring layer in the insulating film; forming an insulating protective film on the copper wiring layer; forming an opening extended to the copper wiring layer in the insulating protective layer; and forming a film of a metal whose oxidation tendency is higher than copper or a film of an alloy containing a metal whose oxidation tendency is higher than copper on the copper wiring layer in the opening while heating, thereby diffusing the metal or the alloy in the copper wiring layer so that an alloy containing copper and a metal whose oxidation tendency is higher than copper extended to the bottom surface of the copper wiring layer is formed to form a pad electrode layer, and an oxide layer mainly comprising the metal on the surface layer of the pad electrode layer is formed.
A semiconductor device according to another embodiment of the invention is comprised of a wiring pad; an insulating film which is formed on the wiring pad and has plural contact holes extended to the wiring pad; and a conducting protective layer which is disposed on the wiring pad via the insulating film and electrically connected to the wiring pad through the plural contact holes.
Another semiconductor device according to another embodiment of the invention is comprised of a insulating film having an opening; plural insulating pillars disposed in the opening; a wiring pad embedded in the opening to extend to its midway; and a conducting protective layer to the wiring pad which is disposed on the wiring pad so to fill the opening.
A semiconductor device according to still another embodiment of the invention is comprised of a wiring disposed in a predetermined pattern above a substrate; a protecting conductive layer disposed on a pad section of the wiring; and a barrier film which is disposed between the wiring and the conducting protective layer and formed by stacking two pairs or more of a layer made of a predetermined metal element and a layer made of a compound mainly comprising the metal element.